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scripting problem

I am trying to make a Makefile which can accept an a c file name as an argument to be used as a variable in my script so that i can use it with any of my c files for compilation .
the content of Makefile as follows..

#!/bin/bash

x=$1
exec: ${x}.o
gcc -o exec ${x}.o
${x}.o: ${x}.c
gcc -c ${x}.o ${x}.c

it is not executing properly as the final executable file is not exec but the with the same name as that of the c file name..i think its using the default makefile to create the executable file .
am i doing it right ?????what is the right make command (to be given) to execute this script…

2 Responses to scripting problem

  1. dhanashri says:

    Above script is correct.
    1) The only change is give tab before gcc. It is must.
    2) While compiling you need to give the command “make your_program_name”
    With above two changes it is expected to work.
    Please try it.

    • hey thanks for the reply
      I had used the tab..
      and by using “make your_program_name” it uses the default makefile and creates the executable file with the same name as of the program instead of creating “exec”

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