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Course: 205.Serial Port Device Driver Development

 

Course Syllabus & Schedule Overview
Week / Module
Module Title
Core Focus Area
Primary Lab Deliverable
Module 1
Physical Layer & Serial Communication Fundamentals
Signals, Voltage Levels, Baud Math, Frames & Datasheet Reading
Logic Analyzer Signal Decoding & Framing Error Simulation
Module 2
16550 UART Architecture & Register Map
Register Bank, DLAB Mechanisms, Trigger Thresholds & FIFOs
Low-Level Register State Visualizer & Diagnostics
Module 3
Bare-Metal 16550 UART Driver Implementation
Polling, IRQ Handlers, Circular Queues & Loopback
Production-Grade Interrupt-Driven Bare-Metal Driver
Module 4
Linux Serial Core Subsystem & TTY Architecture
TTY Layers, Line Disciplines, uart_ops, Device Tree
Device Tree Overlay & Kernel Serial Driver Skeleton
Module 5
Production Linux Driver, Earlycon & DMA
Kernel Module, Platform Driver, Flip Buffers, Debugging
Fully Functional Linux Kernel 16550 Serial Driver
 

Module 1: Physical Layer & Serial Communication Fundamentals

Learning Objectives

• Understand the core distinctions between synchronous and asynchronous serial protocols.
• Analyze physical layer signaling: TTL, RS-232, RS-485 differential signaling, and voltage conversion ICs (e.g., MAX232).
• Read and extract timing parameters, electrical constraints, and register offsets from real hardware datasheets (e.g., NS16550A / PD16550).
• Calculate baud rates, prescalers, fractional error margins, and line parameters given target clock frequencies.
• Identify hardware vs. software flow control mechanisms (RTS/CTS vs. XON/XOFF) and signal line states.

Module 2: 16550 Hardware Architecture & Register Map

Learning Objectives

• Master the 16550 UART internal block structure, register map, and address offset offsets.
• Comprehend the DLAB (Divisor Latch Access Bit) multiplexing mechanics on registers 0x00 and 0x01.
• Program and configure Line Parameters via Line Control Register (LCR).
• Understand hardware FIFO behavior: 16-byte depth, trigger threshold programming via FIFO Control Register (FCR), and timeout interrupts.
• Interrogate status registers (LSR, MSR, IIR) for hardware state diagnosis.

Module 3: Bare-Metal 16550 UART Driver Implementation

Learning Objectives

• Implement raw memory-mapped/IO access macros and register abstractions.
• Write robust polling-based transmission and reception routines with defensive timeout loops.
• Design and implement thread-safe circular ring buffers for interrupt-driven operation.
• Program interrupt enable bits and clear hardware IRQ pending flags cleanly inside Interrupt Service Routines (ISRs).
• Execute hardware self-tests utilizing internal digital Loopback Diagnostic Mode (MCR Bit 4).

Module 4: Linux Serial Subsystem & TTY Architecture

Learning Objectives

• Comprehend the 3-layer architecture of the Linux TTY Subsystem (TTY Core Line Discipline Serial Core Hardware Driver).
• Understand key Linux Kernel structures: struct uart_driver, struct uart_port, and struct uart_ops.
• Bind platform hardware drivers via Device Tree nodes utilizing compatible = "ns16550a".
• Trace character flows from user-space calls (write()) down to hardware THR register pushes.

Module 5: Production Linux Driver, Earlycon & DMA

Learning Objectives

• Build a full Linux Kernel Module implementing a platform driver for 16550 UART hardware.
• Connect the low-level interrupt handler to the TTY flip-buffer subsystem using tty_insert_flip_char.
• Handle dynamic baud rate, word-length, stop-bit, and parity configuration in .set_termios.
• Configure kernel early console (earlycon) support for low-level system debugging.
• Execute production testing using Linux tools (stty, picocom, /proc/tty/driver/).

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