In DTMF we use 8770 ic which decode the dual-tone, multi-frequency send through u’r phone. After this u can program u’r IC to do specified works
In DTMF we use 8770 ic which decode the dual-tone, multi-frequency send through u’r phone. After this u can program u’r IC to do specified works
Each hardware device controller capable of issuing interrupt requests has an output line
designated as an IRQ (Interrupt ReQuest). All existing IRQ lines are connected to the input
pins of a hardware circuit called the Interrupt Controller, which performs the following
actions:
1. Monitors the IRQ lines, checking for raised signals.
2. If a raised signal occurs on an IRQ line:
a. Converts the raised signal received into a corresponding vector.
b. Stores the vector in an Interrupt Controller I/O port, thus allowing the CPU to
read it via the data bus.
c. Sends a raised signal to the processor INTR pin—that is, issues an interrupt.
d. Waits until the CPU acknowledges the interrupt signal by writing into one of
the Programmable Interrupt Controllers (PIC) I/O ports; when this occurs,
clears the INTR line.
3. Goes back to step 1.
Starting with the Pentium model, Intel 80×86 microprocessors introduce extended paging ,
which allows page frames to be either 4 KB or 4 MB in size.Extended paging is enabled by setting the Page Size flag of a Page Directory entry.The paging unit divides the 32 bits of a linear address into two fields:
1.Directory
The most significant 10 bits
2.Offset
The remaining 22 bits
vmalloc allocates a contiguous memory region in the virtual address space. Although the pages are not con-secutive in physical memory (each page is retrieved with a separate call to alloc_page),the kernel sees them as a contiguous range of addresses. vmalloc returns 0 (the NULL address) if an error occurs, otherwise, it returns a pointer to a linear memory area of size at least size.
Memory obtained from vmalloc is slightly less efficient to work with,
and, on some architectures, the amount of address space set aside for vmalloc is rela-
tively small. Code that uses vmalloc is likely to get a chilly reception if submitted for
inclusion in the kernel. If possible, you should work directly with individual pages
rather than trying to smooth things over with vmalloc.
The CPU is connected to memory and various other I/O devices through strips of wires called buses. These buses just take the data, address and control signals from one place to another.
There are three types of buses :-
#1 Data Bus. (Bidirectional)
# 2 Address Bus. (Unidirectional)
#3 Control Bus. (Unidirectional)
The data bus is used for carrying data in and out from the CPU. The data bus determines the performance of the CPU, more the data lines in a data bus better is the CPU. The average size of data bus varies from 8 bit to 64 bit.
The address bus is used to identify the device and memory connected to CPU. If CPU wants to communicate with device or a memory, it just loads its address on the address bus and device or location having that add becomes active.
The control bus is used for sending control signal to the addressed device or memory for performing read and write operations at that location.
with the help of UM3561 we can create 3 different tone.
pin 1 and pin 6 are selecting pins to create different tones
Besides general-purpose hardware caches, Intel 80×86 processors include other caches called translation lookaside buffers or TLB to speed up linear address translation. When a linear address is used for the first time, the corresponding physical address is computed through slow accesses to the page tables in RAM. The physical address is then stored in a TLB entry, so that further references to the same linear address can be quickly translated.
The invlpg instruction can be used to invalidate (that is, to free) a single entry of a TLB. In
order to invalidate all TLB entries, the processor can simply write into the cr3 register that
points to the currently used Page Directory.
in smoke sensor we need mq2 sensor and lm324 ic .
with the help of variable register we can vary the resistivity of the sensor
In order to manage processes, the kernel must have a clear picture of what each process is
doing. It must know, for instance, the process’s priority, whether it is running on the CPU or
blocked on some event, what address space has been assigned to it, which files it is allowed to address, and so on. This is the role of the process descriptor , that is, of a task_struct type
structure whose fields contain all the information related to a single process. As the repository of so much information, the process descriptor is rather complex. Not only does it contain many fields itself, but some contain pointers to other data structures that, in turn, contain pointers to other structures.
#include<stdio.h>
#include<malloc.h>
int main()
{
int r,c,i,j,**p;
printf(“How many rows,you want to insert: “);
scanf(“%d”,&r);
printf(“How many columns,you want to insert: “);
scanf(“%d”,&c);
p=malloc(r*c*sizeof(int));
printf(“Enter your %d*%d matrix elements: “,r,c);
for(i=0;i<r;i++)
{
for(j=0;j<c;j++)
scanf(“%d\n”,&(*(*(p+i)+j)));
}
for(i=0;i<r;i++)
{
for(j=0;j<c;j++)
printf(“%d”,*(*(p+i)+j));
}
}
For the sake of efficiency, linear addresses are grouped in fixed-length intervals called pages;
contiguous linear addresses within a page are mapped into contiguous physical addresses. In
this way, the kernel can specify the physical address and the access rights of a page instead of
those of all the linear addresses included in it. Following the usual convention, we shall use
the term “page” to refer both to a set of linear addresses and to the data contained in this group of addresses.
The paging unit thinks of all RAM as partitioned into fixed-length page frames (they are
sometimes referred to as physical pages). Each page frame contains a page, that is, the length
of a page frame coincides with that of a page. A page frame is a constituent of main memory,
and hence it is a storage area. It is important to distinguish a page from a page frame: the
former is just a block of data, which may be stored in any page frame or on disk.
The paging unit thinks of all RAM as partitioned into fixed-length page frames (they are
sometimes referred to as physical pages). Each page frame contains a page, that is, the length
of a page frame coincides with that of a page. A page frame is a constituent of main memory,
and hence it is a storage area. It is important to distinguish a page from a page frame. the
former is just a block of data, which may be stored in any page frame or on disk.
The data structures that map linear to physical addresses are called page tables. they are
stored in main memory and must be properly initialized by the kernel before enabling the
paging unit.
To allow an efficient search through processes of a given type (for instance, all processes in
a runnable state) the kernel creates several lists of processes. Each list consists of pointers to
process descriptors. A list pointer (that is, the field that each process uses to point to the next
process) is embedded right in the process descriptor’s data structure. When you look at
the C-language declaration of the task_struct structure, the descriptors may seem to turn in
on themselves in a complicated recursive manner. However, the concept is no more
complicated than any list, which is a data structure containing a pointer to the next instance of itself.
A logical address consists of two parts: a segment identifier and an offset that specifies the
relative address within the segment. The segment identifier is a 16-bit field called Segment
Selector, while the offset is a 32-bit field.
To make it easy to retrieve segment selectors quickly, the processor provides segmentation
registers whose only purpose is to hold Segment Selectors; these registers are called cs, ss,
ds, es, fs, and gs.
Flash devices, including NOR flash devices such as CFI flash chips and NAND flash
devices such as the DOC, are not like disk storage devices. They cannot be written to
and read from arbitrarily. To understand how to operate flash chips properly, we must
first look at how they operate internally. Flash devices are generally divided into erase
blocks. Initially, an empty block will have all its bits set to 1. Writing to this block
amounts to clearing bits to 0. Once all the bits in a block are cleared (set to 0), the only
possible way to erase this block is to set all of its bits to 1 simultaneously. With NOR
flash devices, bits can be set to 0 individually in an erase block until the entire block is
full of 0s. NAND flash devices, on the other hand, have their erase blocks divided further
into pages, of 512 bytes typically, which can only be written to a certain number of times
—typically less than 10 times—before their content becomes undefined. Pages can then
only be reused once the blocks they are part of are erased in their entirety
