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PCI Device Driver

Abstract:

During the early 1990s, Intel introduced a new bus standard for consideration, the Peripheral Component Interconnect (PCI) bus. The PCI bus was defined to establish a high performance and low cost local bus that would remain through several generations of products. The original version of the PCI bus is 32-bits wide and has a clock speed of 33 MHz, which allows it to theoretically provide a throughput of 132 Mb/s on 32 bits. On 64-bit architectures, the bus operates on 64 bits and offers a theoretical throughput of 264 Mb/s. The disadvantage of the PCI bus is the limited number of electrical loads it can drive. A single PCI bus can drive a maximum of 10 loads.

Introduction::

The Peripheral Component Interconnect - Bus (PCI) today is present in a wide variety of microcomputers ranging from Intel-based PC architectures to DEC-Alpha-based work- CPU Memory stations. The main difference between the old fashioned ISA-Bus and PCI is the complete separation of the Bus-subsystem from the Memory Subsystem. The CPU communicates with the PCI subsystem using a special chipset known as PCI-Bridge. This is an intelligent controller, that handles all necessary tasks to transfer data from or to the CPU or the Memory Subsystem. On PCI the adresses and data are transferred as seperate chunks over the bus because all bus lines can be used either as adress- or as data-lines. In special cases only one start address is transferred followed by a whole data block. All read and write on pci bus can be performed as burst transfers. The length of the burst is determined by the bus master. Each burst transfer consist of the following basic components.

  • The address and transfer type are output during the address phase.

  • A data object (upto 32-bits in a 32 bit implementation or 64-bits in a 64 bit implementation ) may then be transferred during each subsequent data phase.

    Each PCI peripheral is identified by a bus number, a device number, and a function number. The PCI specification permits a single system to host up to 256 buses, but because 256 buses are not sufficient for many large systems, Linux now supports PCI domains. Each PCI domain can host up to 256 buses. Each bus hosts up to 32 devices, and each device can be a multifunction board with a maximum of eight functions.

Configuration Space

Each PCI device has a block of 256 bytes of configuration space: 16 32-bit doublewords of header information plus 48 doublewords of device-specific configuration registers.

Configuration space is completely separate from memory and I/O space, and can only be accessed using the PCI bus Configuration Read and Write commands. PCI specification defines two methods by which this can be achieved. The preferred method, used by current implementations, is to write the target address to the 32-bit I/O port at 0CFBh, and then read or write the doubleword through I/O port 0CFCh. A second method, used by early PCI chip sets but now discouraged by the PCI specification, involves using I/O ports at 0CF8h and 0CFAh to map the configuration spaces of up to 16 PCI devices into the I/O range C000h to CFFFh, from where the data may be read or written.

Some Features of PCI bus-subsystem are

  • The PCI bus has three separate address spaces, config, I/O, and memory space.
  • Every PCI device responds to config commands, and it can respond to I/O accesses
  • and/or memory accesses.
  • During the boot time, the BIOS or the OS sets the base address registers (BARs)
  • through configuration space.
  • BARs determine address ranges in I/O or memory space that a device should respond to.
  • There can be multiple PCI hostbridges on some systems.
  • Multiple PCI buses can be connected through PCI-to-PCI bridges.
  • Some variant of the PCI bus support hot plugging.

Prospects:

With the rapid development of computer,PCI bus is considered to be incapable of affording the demanding of I/O bus bandwidth. There are two ways to process, named PCI-X bus and PCI Express bus. The market of server is occupied by PCI-X now a days. PCI Express is considered to be the dominant I/O bus in computer industry in the future.

Training Objective:

This course is designed to ensure that students of Engineering College with academic capabilities will have the skill set needed to deal with the challenges involved in real-world Embedded Technologies and Devices Design to meet the needs of industries both today and in the future.

The course considers programming and device design techniques which can help to ensure that single-processor embedded systems are reliable.

The course is taught mainly using the  C programming language, hardware design, ARM Based Board and a PC emulated as an embedded device.

Pre-requisites:

  • General understanding about Computer Architecture, Operating System Concepts and C Programming Language is assumed.
  • A prior knowledge or exposure to Linux operating system would be an added advantage.
  • Must Have Implementes atleast a Character Driver and a Block Driver.

Agenda:

  • The Duration of Training is:

    • The Duration of Training would be 2 weeks
    • There would be 8 Classroom Sessions of 2 Hrs each
    • 8 Lab Sessions of 4 hrs each
  • The course is split into eight modules: (as described below)

Training Topics in Brief:

  • PCI device_id structure creation.
  • Exporting device_id structure to user space to allow hot-plugging.
  • Probe function which will be called by core when it has a struct pci_dev that it thinks this driver wants to control.
  • Enabling the PCI device.
  • Accessing the configuration spaces.
  • Accessing I/O and Memory spaces.
  • Remove function called by core when struct pci_dev is being removed from the system.
  • Registration of pci_driver structure with kernel pci_register_driver.

     

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