Innovation... driven by intelligence and logic

Serial Port Device Driver Development

Abstract:

The training program on Serial Port Device Driver Development aims at creating the driver from scratch. During the training, we would discuss in detail about data-sheet interpretation, underatanding the architecture of the serial port and the assicoated chip PC16550D, underatanding serial IO, RS232 protocol. Then the driver development would start.


Training Topics in brief: 

  • Introduction to Serial Port
  • Detailed discussion on RS232 Protocol
  • Microscopic understanding of serial port chip
  • DataSheet Interpretetion
  • Introduction to Serial Port Device Driver
  • Registering the driver and accessing the IO
  • Device IO Operations using Serial Port Driver
  • Establishing Serial Communication between Devices Byte Transfer
  • Device Driver for the cross connection
  • Using Interrupts for Serial Communication
  • Using FTP to transfer files
  • Establishing Serial Communication between Devices: Two way Communication

Salient Features of Training Program

Training Objective:

  • This short course is designed to ensure that the trainees with academic capabilities will have the skill set needed to deal with the challenges involved in real-world device driver design using Linux to meet the needs of industries both today and in the future.
  • Understand RS232 Protocol, Serial Port, UART chip.
  • Learn Datasheet interpretation
  • Design and Write a serial port device driver for serial port chip with FIFO and implement bacic operations through the driver.

Pre-requisite:

  • Education: ​BE, B Tech in ECE, EEE, CSE, IT or MCA
  • Good understanding of C programming language and Shell Scripting using Bash
  • Knowledge of Linux Kernel internal and Device Driver Architecture
  • ​The trainee must have already implemented the character device driver

Agenda:

The Duration of Training would be:
  • The Duration of training would be 7 working days.
  • There would be
    • 5 Classroom Sessions of 2 hours each
    • 10 Lab of 4 hours each
    • 50 hours of training.
Training Methodology:
  • Hands on approach to training, behaviorial model of training would be practiced.
  • During the training, the Trainee would implement a projects related to respective modules.
  • Comitment to Individual growth and constant evaluation.
  • Implementation of programming techniques through a Project.

Deliverables:

After the training is over, the Trainee should be able to:-

  • Understand the RS232 protocol
  • Understand the Serial port driver architecture for Linux
  • do data-sheet interpretatoin for the serial port chip
  • write the serial port device driver for PC16550D UART with FIFO from scratch.

EmbLogic would issue/provide the following:-

  • Project Report for Submitting into their college.
  • Project presentaation and demonstration assistance.
  • Completed Project (by the trainee).
  • Certificate of Completion for the training and Project as mentioned above.

Introduction:

The PC16550D is an improved version of the original 16450 Universal Asynchronous Receiver Transmitter (UART) Functionally identical to the 16450 on powerup (CHARACTER mode) the PC16550D can be put into an alternate mode (FIFO mode) to relieve the CPU of excessive software overhead In this mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes All the logic is on chip to minimize system overhead and maximize system efficiency Two pin functions have been changed to allow signalling of DMA transfers.
The UART performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM and parallel-to-serial conversion on data characters received from the CPU The CPU can read the complete status of the UART at any time during the functional operation Status information reported includes the type and condition of the transfer operations being performed by the UART as well as any error conditions (parity overrun framing or break interrupt)
The UART includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216b1) and producing a 16 c clock for driving the internal transmitter logic Provisions are also included to use this 16 c clock to drive the receiver logic The UART has complete MODEM-control capability and a processor-interrupt system Interrupts can be programmed to the user’s requirements minimizing the computing required to handle the  communications link The UART is fabricated using National Semiconductor’s advanced M2CMOS process.

Synopsys:

Serial Port Device Driver

The UART performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM and parallel-to-serial conversion on data characters received from the CPU The CPU can read the complete status of the UART at any time during the functional operation Status information reported includes the type and condition of the transfer operations being performed by the UART as well as any error conditions (parity overrun framing or break interrupt)

The UART includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216b1) and producing a 16x clock for driving the internal transmitter logic Provisions are also included to use this 16x clock to drive the receiver logic The UART has complete MODEM-control capability and a processor-interrupt system Interrupts can be programmed to the user’s requirements minimizing the computing required to handle the communications link The UART is fabricated using National Semiconductor’s advanced M2CMOS process.

This Project aims at writing a device driver for PC16550D UART chip and transferring data between the systems through serial port using RS232 protocol. It also involves the Data sheet interpretation for understanding the device registers . Firstly the baud rate was set between the systems. Then the corresponding registers are configured. For transmission and reception of large amount of data FIFO is used along with DMA . The system's internal layers iwere synchronized using Kernel timers and Blocking i/o .


Training and projects Resources   Click here...


EmbLogicTM is an ISO 9001:2008(QMS) (Quality Management System) Certified Company

 

 

Go to Top ^
+91-9818467776
We can call you