EmbLogic » makefile https://www.emblogic.com/blog Embedded System and ARM Training Tue, 03 Mar 2020 13:00:06 +0000 en-US hourly 1 http://wordpress.org/?v=3.9.1 scripting problem https://www.emblogic.com/blog/03/scripting-problem/ https://www.emblogic.com/blog/03/scripting-problem/#comments Fri, 30 Mar 2012 15:02:20 +0000 http://emblogic.org/blog/?p=2302 Continue reading →]]> I am trying to make a Makefile which can accept an a c file name as an argument to be used as a variable in my script so that i can use it with any of my c files for compilation .
the content of Makefile as follows..

#!/bin/bash

x=$1
exec: ${x}.o
gcc -o exec ${x}.o
${x}.o: ${x}.c
gcc -c ${x}.o ${x}.c

it is not executing properly as the final executable file is not exec but the with the same name as that of the c file name..i think its using the default makefile to create the executable file .
am i doing it right ?????what is the right make command (to be given) to execute this script…

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