SPI (Serial Peripheral Interface) bus, which is commonly used for communication between integrated circuits or sensors .It is a serial master-slave Synchronous Protocol . It comes built in on many microcontrollers and SOC. The SPI serial bus was originally established by Motorola. Today, it is one of the most common communication buses used by integrated circuit manufactures for device to processor or FPGA control. Examples include ADCs, DACs, sensors, and board-only products. I
Although it is not regulated as a standard by IEEE or another organization, most devices adhere to common set of rules described .

SPI is a synchronous serial data link that operates in full duplex. That is, signals carrying data go in both directions simultaneously. Devices communicate using a master/slave protocol, in which the
master starts the data frame. When the master generates a clock then selects a slave device, data may be transferred in either or both directions simultaneously. It is up to the master and slave devices to know whether a received byte is meaningful. This may require a device to discard the received byte in a transmit only” frame or generate a dummy byte for a “receive only” frame.

It uses four wires Serial ClocK (SCLK), Chip Select (CS), Master Out Slave In (MOSI), Master In Slave Out (MISO).

Basic Connections :-
The four typical SPI signals include:
clock (SCLK) – This signal is generated by the Master. Other signals in the transmission change based on the timing of edges from this clock.
master data output, slave data input (MOSI) – This line is the output from the Master to the slave. Transmits bit-by-bit synchronized with Master clock edges.
master data input, slave data output (MISO) – This line is the output from all the slaves connected. Transmits bit-by-bit from the slave synchronized with Master clock edges.
chip select (CS) or slave select (SS) – This is a bank of signals where each line goes to individual slaves in the system. One line is asserted at a time to enable communicate with the corresponding slave.

MOSI is used for shifting data into the slave device, and MISO is used for shifting data out of the slave device. Because the SPI bus has dedicated wires for transmitting and receiving data, it can operate in full-duplex mode, unlike the I 2C bus. The typical speed of
operation of SPI is in the low-megahertz range, unlike the mid-kilohertz range on I2C, so the former yields higher throughput.
SPI peripherals available in the market today include Radio Frequency (RF) chips, smart card interfaces, EEPROMs, RTCs, touch sensors, and ADC

Basic Transmission Step-by-Step
1. The Master drives a particular SS line low to initiate communication with the corresponding slave.
2. Once the selected SS is low, one edge (rising or falling) of the SCLK signals the devices (Master and Slave) to toggle the MOSI and MISO to the correct bit of data being transmitted.
3. The other edge of the SCLK line (rising or falling) signals the devices to register the bits on the MOSI and MISO, effectively reading the bit into the device.
4. The transmission continues in this fashion until the devices have exchanged the specified number of bits (usually 8,16, or 32)
5. After the transmission is complete the Master pulls the SS line for the slave back high and either goes to another slave on the network or reinitiates the transmission with the same slave by
pulling the corresponding1 SS line back to low.

2.BULIDDIR:- It is in this directory that will compile all source packages e.g.
export BUILDDIR=/root/chaine/build
3.TARGETMACH:-
This variable specifies the type of target architecture
e.g.
export TARGETMACH=arm-none-linux-gnueabi
4.BUILDMACH:-
This variable specifies the type of architecture in which the package is compiled.

export BUILDMACH=x86_64-pc-linux-gnu
5.INSTALLDIR
This variable provides information about the folder hosting the cross-toolchain.

export INSTALLDIR=/opt/arm

6.SYSROOTDIR :-
This variable provides information on the directory hosting the libraries and header files the kernel of the target system.e.g.
export SYSROOTDIR=/opt/arm/sysroot

7.CROSS:-
Indicates that we use the variable fields CROSS with arm-none-linux-gnueabi.
export CROSS=arm-none-linux-gnueabi

An embedded USB device that switches roles, referred as dual role device, has features that include minimal USB host capability, Session Request Protocol (SRP), Host Negotiation Protocol (HNP), and 8mA on VBUS.

Linux has a simple infrastructure to support OTG devices. The OTG infrastructure is much closer to the hardware, similar to the peripheral device controller (PDC) driver, the OTG framework is responsible for handling
and responding to the OTG protocol negotiations such as SRP and HNP.broad level, the functionality of the OTG framework controls the USB transceiver hardware to meet the OTG requirement.

OTG Driver Framework
The OTG framework is not clearly defined like the gadget framework is sometimes the OTG implementation is mixed with the other frameworks. The Linux USB subsystem source code of OTG framework is maintained in the
/drivers/usb/otg/ folder. Some part of the usbcore module plays a key role (drivers/usb/core/hub.c). Most of the OTG activities are based on the physical layer activity and the timing of the electrical signals. The role of OTG software framework is minimal .It is responsible for setting up the signal and switching to different states defined by the OTG specification .
The OTG framework is divided into two major parts: callback methods and utility functions. The methods provided by struct otg_tranceiver are extended to the other Linux USB frameworks using wrapper functions. The OTG
framework also helps save and retrieve the struct otg_transceiver object using utility functions. The other main part is interface methods of the transceiver to platform.

The OTG driver flow consists of both the host and the device driver framework, taking its part to switch the role by using the OTG framework. Like the PDC driver, the OTG driver is specific to the hardware and the platform
for which the transceiver is developed. OTG driver starts by registering itself successfully with the Linux platform, along with the platform callbacks such as probe routine. The platform calls the registered probe routine when it detects transceiver. The probe routine maps the platform resource and creates the struct otg_transceiver object. The probe routine also sets the callbacks of otg_transceiver. Once the probe is successful, the OTG framework is functionally ready for the host and gadget framework to use it.

NO Matter of size but Life is on the Earth so all Emblogician who are going and preparing to face the World .Don’t afraid from the world, World is for you . Move ahead and conquer entire world with your knowledge and humble through your entire Life .

H.264/MPEG-4 AVC is a block-oriented motion- compensation -based codec standard .CONTEXT-BASED adaptive binary arithmetic coding (CABAC) used in H.264/AVC , is an extension of the binary arithmetic coding (BAC), where the coding offset value is dynamically adjusted based on the syntax element being encoded/decoded. While the coding efficiency of CABAC is superior to the conventional Huffman coding , the improvement comes with an increasing performance requirement; at least 3 GHz of computing power is required for the real-time decoding of a HD sequence if a general-purpose,yet high-speed, RISC machine processes the syntax parsing.As HD digital TV broadcasting coded in H.264/AVC Main Profile and High Profile is being widely spread at the present,the necessity of a high-speed CABAC decoder is growing

The gained insights are finally used to optimize the run time behavior of a multi-core decoding system and to find a good trade-off between core usage and buffer sizes.

Increasing the coding efficiency of video codecs with the common combination of temporal prediction and lossy transform coding is basically a matter of reducing the remaining redundancy in the data streams. In H.264 standard, this goal has been achieved by means of more advanced pixel processing algorithms (eg 1/4-pixel motion estimation)as well as using more sophisticated algorithms for predicting syntax elements from neighboring macro blocks (eg context adaptive VLC). However, the advanced coding tools result in significantly increased CPU and memory loads on encoder as well as the decoder. The high computational demands pose a challenge for practical H.264 implementations in environments of limited processing power such as mobile devices. Understanding the run time behavior of the H.264 decoder is therefore essential for meeting the desired performance requirements on the underlying platform. If the computational requirements of a video algorithm cannot be met with a single processing unit, multi-core systems often provide an elegant and power-efficient alternative. Unfortunately,efficiently distributing the video algorithm among multiple processing units is a non-trivial task. It requires detailed knowledge about the algorithmic complexity and inter-dependencies between functional blocks. The most severe problem, however, is that there are strong dynamic variations in run time on the basic level of the H.264 decoding process, namely the level of macro blocks. We go into more detail on this dynamic behavior in the following. Roughly spoken, an H.264 stream can be regarded as a sequence of compressed macro blocks. In the decoding process, each macro block is sent through the decoder pipeline one after the other in order to derive the uncompressed video information. When looking at the computation time consumed by each macro block, it is observed that there are large variations.

USB is a master-slave protocol where a host controller communicates with client devices. The USB host controller is part of the South Bridge chipset and communicates with
the processor over the PCI bus.

Usb types :-

Usb types Connectors bases :-

There are four basic kinds or sizes related to the USB connectors
1. The older “standard” size, in its USB 1.1/2.0 and USB 3.0 variants eg. usb pendrive
2. The “mini” size (primarily for the B connector ) e.g. Cemra
3. The “micro” size, in its USB 1.1/2.0 and USB 3.0 variants eg. In mobile phone .
4. USB On The Go scheme, in both mini and micro sizes.

Usb types Speed bases :-

1. USB 1.x
USB 1 specified data rates of 1.5 Mbits/s Low-Bandwidth and 12 Mbits/s Full-Bandwidth. It is generally white color.
2. USB 2.0
USB 2.0 is adding higher maximum signaling rate of 480 Mbits Hi-Speed.USB 2.0 connectors are black.

3. USB 3.0
The standard defines a new Super Speed mode with a signaling speed of 5Gbits/s. USB 3.0 port is usually colored blue, and is backwards compatible with USB 2.0

Host Controllers
:-
USB host controllers conform to one of a few standards:

Universal Host Controller Interface (UHCI): The UHCI specification was initiated by Intel, so our
is likely to have this controller if it’s Intel-based.
Open Host Controller Interface (OHCI): The OHCI specification originated from companies such as
Compaq and Microsoft. An OHCI-compatible controller has more intelligence built in to hardware than
UHCI, so an OHCI HCD is relatively simpler than a UHCI HCD.
Enhanced Host Controller Interface (EHCI): This is the host controller that supports high-speed USB
2.0 devices. EHCI controllers usually have either a UHCI or OHCI companion controller to handle slower
devices.
USB OTG controllers: They are getting increasingly popular in embedded microcontrollers. With OTG
support, each communicating end can act as a dual-role device (DRD).

eXtensible Host Controller Interface (xHCI): This is a computer interface specification that defines a register-level description of a Host Controller for Universal Serial bus (USB), which is capable of interfacing to USB 1.x, 2.0, and 3.0 compatible devices. The specification is also referred to as the
USB 3.0 Host Controller

you can check host controllers by the following command
[root@localhost ubh3b]# lspci
00:00.0 Host bridge: Intel Corporation Ivy Bridge DRAM Controller (rev 09)
00:01.0 PCI bridge: Intel Corporation Ivy Bridge PCI Express Root Port (rev 09)
00:01.1 PCI bridge: Intel Corporation Ivy Bridge PCI Express Root Port (rev 09)
00:02.0 VGA compatible controller: Intel Corporation Device 0166 (rev 09)
00:14.0 USB Controller: Intel Corporation Panther Point USB xHCI Host Controller (rev 04)
00:16.0 Communication controller: Intel Corporation Panther Point MEI Controller #1 (rev 04)
00:1a.0 USB Controller: Intel Corporation Panther Point USB Enhanced Host Controller #2 (rev 04)
00:1b.0 Audio device: Intel Corporation Panther Point High Definition Audio Controller (rev 04)
00:1c.0 PCI bridge: Intel Corporation Panther Point PCI Express Root Port 1 (rev c4)
00:1c.1 PCI bridge: Intel Corporation Panther Point PCI Express Root Port 2 (rev c4)
00:1d.0 USB Controller: Intel Corporation Panther Point USB Enhanced Host Controller #1 (rev 04)
00:1f.0 ISA bridge: Intel Corporation Panther Point LPC Controller (rev 04)
00:1f.2 SATA controller: Intel Corporation Panther Point 6 port SATA AHCI Controller (rev 04)
00:1f.3 SMBus: Intel Corporation Panther Point SMBus Controller (rev 04)
01:00.0 3D controller: nVidia Corporation Device 1140 (rev a1)
03:00.0 Ethernet controller: Atheros Communications Device 1090 (rev 10)
04:00.0 Network controller: Atheros Communications Inc. AR9485 Wireless Network Adapter (rev 01)

Transfer Types
:-
Data exchange with a USB device can be one of four types:
1. Control transfers :- used to carry configuration and control information
2. Bulk transfers :-that ferry large quantities of time-insensitive data
3. Interrupt transfers:- that exchange small quantities of time-sensitive data
4. Isochronous transfers :- for real-time data at predictable bit rates

A USB storage drive, for example, uses control transfers to issue disk access commands and bulk transfers to exchange data. A keyboard uses interrupt transfers to carry key strokes within predictable delays. A device that
needs to stream audio data in real time uses isochronous transfers.

Addressing
Each addressable unit in a USB device is called an endpoint. The address assigned to an endpoint is called an
endpoint address. Each endpoint address has an associated data transfer type. If an endpoint is responsible for
bulk data transfer, for example, it’s called a bulk endpoint. Endpoint address 0 is used exclusively for device
configuration. A control pipe is attached to this endpoint for device enumeration.
Enumeration
The life of a hotplugged USB device starts with a process called enumeration by which the host learns about the
device’s capabilities and configures it. The hub driver is the component in the Linux-USB subsystem responsible
for enumeration. Let’s look at the sequence of steps that achieve device enumeration when you plug in a USB
pen drive into a host computer:
1. The root hub reports a change in the port’s current due to the device attachment. The hub driver detects
this status change, called a USB_PORT_STAT_C_CONNECTION in Linux-USB terminology, and awakens khubd.
2. Khubd deciphers the identity of the USB port subjected to the status change. In this case, it’s the port
where you plugged in the pen drive.
3. Next, khubd chooses a device address between 1 and 127 and assigns it to the pen drive’s bulk endpoint
using a control URB attached to endpoint 0.
4. Khubd uses the above control URB attached to endpoint 0 to obtain the device descriptor from the pen
drive. It then requests the device’s configuration descriptors and selects a suitable one. In the case of the
pen drive, only a single configuration descriptor is on offer.
5. Khubd requests the USB core to bind a matching client driver to the inserted device.
When enumeration is complete and the device is bound to a driver, khubd invokes the associated client driver’s
probe() method. In this case, khubd calls storage_probe() defined in drivers/usb/storage/usb.c. From this
point on, the mass storage driver is responsible for normal device operation.

Please join this thread for your all grievances and issues for up-mentioned topics

Regards and thanks
Dharmendra Nath Shandilya

Today entire Team works on Prob.

Please all Team E2 members join this thread for not for your grievances and issues,only daily report will attached with this thread.
For your grievances and issues please follows ‘E2- USB DRIVER Problems and Solution’ in USB Driver categories.

Regards and thanks
Dharmendra Nath Shandilya

Please join this thread for your all grievances and issues for up-mentioned topics

Regards and thanks
Dharmendra Nath Shandilya

Thanks and Regards
Dharmendra Nath Shandilya
&
Purnendu

Thanks and regards
Dharmendra Nath Shandilya

Thanks and regards
Dharmendra Nath Shandilya

Thanks and regards
Dharmendra Nath Shandilya

Thanks and regards
E2

Please submit all your details of current Project(Block_driver)
on thread by giving comments from today on-wards.

Thanks & regards
Dnath